For example, Japanese Patent Application Laid-Open Publication No. 2008-28916 discloses a four-terminal double insulated gate field effect transistor (FTMOST) having two insulated gates (first gate and second gate) provided so as to face each other across a channel and electrically insulated from each other. R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, “Silicon on Thin Box: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control”,” IEDM Tech. Dig., 2004, pp. 475-478 discloses a MOS transistor referred to as an SOTB (Silicon On Thin Buried Oxide) MOS transistor (SOTBMOST) that is formed on a semiconductor layer on a thin buried oxide film provided on a semiconductor substrate, that is, an SOI (Silicon On Insulator), wherein a front surface gate is used as a first gate and a back gate in a semiconductor region under the thin buried oxide film electrically insulated from the first gate is used as a second gate.
Note that the SOTBMOST may be structurally regarded as the FTMOST, and a threshold voltage viewed from the first gate can be controlled by the potential applied to the second gate. Therefore, hereinafter, the MOS transistor including SOTBMOST will be referred to as a four-terminal double insulated gate field effect transistor (FTMOST) unless otherwise specified.
Meanwhile, there is a multiplexer using the above-described MOS transistor as a pass transistor. In such a multiplexer, a control signal is already applied at the time when an input logic signal is applied. Namely, which input node has been selected is determined in advance. Therefore, there is a demand for reduction of a propagation delay time taken from the application of the input logic signal to the selected input node to the output of the signal to an output node QM via a selected signal path or a demand for increase in the transfer rate (indicated by frequency) represented by the reciprocal of the propagation delay time.
Here, the propagation delay time is determined by the capacitance between the drain or source of each pass transistor constituting the signal path and the ground (GND). In other words, the smaller the capacitance, the shorter the propagation delay time can be. The capacitance, however, is substantially determined by transistor dimensions, and thus is difficult to control.
Japanese Patent Application Laid-Open Publication No. 2008-28916 describes a method of reducing the propagation delay time by a circuit configuration with respect to the pass transistor formed by the FTMOST. Specifically, one end of a resistor R is connected to the second gate, and the other end of the resistor is connected to a threshold voltage control node VTCN of the FTMOST (see FIG. 27). Alternatively, in a case where two pass transistors PFT1 and PFT2 are connected in series, the second gates of the pass transistors are commonly connected and are further connected to one end of the resistor R, and the other end of the resistor is connected to the threshold voltage control node VTCN of the two FTMOSTs (see FIG. 28). However, none of these is application for a pass transistor in a multiplexer. Moreover, although these state that the propagation delay time can be reduced by the control signal applied to each of the gates, such operation is not possible in the multiplexer because the constant potential is already applied to the gate in the multiplexer.
Note that Japanese Patent Application Laid-Open Publication No. 2006-166384 describes that a resistor is connected between a second gate of the FTMOST and a voltage source for controlling the threshold voltage such that an operation speed of a circuit is improved by an input signal applied to a first gate in a gate circuit or a memory circuit using FTMOST.